What is Unateness in Static Timing Analysis?

Timing Sense corresponds to the functionality of the standard cells. It explains the traversal of a data from the source pin of the gate to its sink pin. Timing sense is also called as unateness of the timing arc.

All the standard cells can be classified based on the unateness they possess. Positive unate, Negative unate and Non-unate are the three types of unateness.

Under the timing section of a standard cell in a .lib file, you can find timing sense information.  

Positive unate: The rise transition at the source pin causes rise transition or no transition at the sink pin and fall transition at the source pin causes fall transition or no transition at the sink pin.

Standard Cells like AND Gate, OR gate, buffer possess this property.

Consider the truth table of AND Gate:

Consider the 1st case of inputs where both A and B are at logic 0 and output is at logic 0. Now consider B is getting transition to logic 1 then the output remains at logic 0 only (no transition). Now let A change to logic 1 then the output also transitions to logic 1.

Negative unate timing arc: The rise transition at the source pin causes fall transition or no transition at the sink pin and fall transition at the source pin causes rise transition or no transition at the sink pin.

Standard Cells like NAND Gate, NOR gate, inverter possess this property.

Consider the truth table of Inverter:

Signal transition on input A makes an opposite transition on the output pin Y.

Non unate: A standard cell which does not possess either of the property is said to be non-unate. XOR and XNOR gates have non-unate timing arcs.

Consider the truth table of XOR Gate :

Consider the 1st case of inputs where both A and B are at logic 0 and output is at logic 0. Now consider B is getting transition to logic 1 then the output changes to logic 1. Consider the 3rd row, where output is at logic 1 with A at logic 1 and B at logic 0, now let B change to logic 1 then the output transitions to logic 0. The gate does not possess either of the property. Hence the timing sense of XOR gate is non-unate.