Verification Vs Validation In VLSI

 

State of the art SOC designs is so complex that, coming up with a bug-free design is very difficult. So chip design flow incorporates several steps to identify the bugs in the earlier stages as well as, in the later stages.

Verification and Validation, both probe for the correctness of the design against the specification by identifying and localizing the bugs in the system, but at different stages in the design cycle. Verification is a pre-silicon process of checking the functionality of the design by simulating it whereas, Validation is a post-silicon process of finding bugs in a few initially manufactured prototypes in the context of a system.

Verification

Functional verification is the process of demonstrating the functional correctness of an RTL design with respect to the design specifications. Functional verification attempts to check whether the proposed design is doing what it is intended to do. This is a complex task and takes the majority of time and effort in most large electronic system design projects. It is imperative that the design is functionally verified and any potential bug is eliminated at an early stage.

It is very common that more engineers’ time and expense is spent to verify a design than the rest of the steps in the ASIC design cycle. Even with this large expenditure, most designs are first fabricated with several bugs still in them. So here comes the importance of Validation.

Validation

While pre-silicon verification runs the test cases on the design on the simulator, post-silicon validation is executed on a few initial hardware prototypes of the design on the silicon chip in a real environment. This process captures the bugs that are escaped during the RTL Design Verification phase. Validation also checks for the correctness of the design but on the real hardware in an actual working ambience.

When a design is passed through all the steps in the design cycle, a few initial prototypes are fabricated as test prototypes. These prototypes are mounted on a test board in a real working environment with real test speed. Identifying bugs through validation is a very fast process as compared to the design verification process but it is difficult to debug the design as there is no way to access the internal signals.

What is Unateness in Static Timing Analysis?

Timing Sense corresponds to the functionality of the standard cells. It explains the traversal of a data from the source pin of the gate to its sink pin. Timing sense is also called as unateness of the timing arc.

All the standard cells can be classified based on the unateness they possess. Positive unate, Negative unate and Non-unate are the three types of unateness.

Under the timing section of a standard cell in a .lib file, you can find timing sense information.  

Positive unate: The rise transition at the source pin causes rise transition or no transition at the sink pin and fall transition at the source pin causes fall transition or no transition at the sink pin.

Standard Cells like AND Gate, OR gate, buffer possess this property.

Consider the truth table of AND Gate:

Consider the 1st case of inputs where both A and B are at logic 0 and output is at logic 0. Now consider B is getting transition to logic 1 then the output remains at logic 0 only (no transition). Now let A change to logic 1 then the output also transitions to logic 1.

Negative unate timing arc: The rise transition at the source pin causes fall transition or no transition at the sink pin and fall transition at the source pin causes rise transition or no transition at the sink pin.

Standard Cells like NAND Gate, NOR gate, inverter possess this property.

Consider the truth table of Inverter:

Signal transition on input A makes an opposite transition on the output pin Y.

Non unate: A standard cell which does not possess either of the property is said to be non-unate. XOR and XNOR gates have non-unate timing arcs.

Consider the truth table of XOR Gate :

Consider the 1st case of inputs where both A and B are at logic 0 and output is at logic 0. Now consider B is getting transition to logic 1 then the output changes to logic 1. Consider the 3rd row, where output is at logic 1 with A at logic 1 and B at logic 0, now let B change to logic 1 then the output transitions to logic 0. The gate does not possess either of the property. Hence the timing sense of XOR gate is non-unate.  

How To Choose Frontend Vs. Backend? A guide for Freshers

 

#VLSI frontend and backend are nothing but two different domains in the field of VLSI.

The classification is based on the different steps involved in a typical ASIC design flow. The following diagram shows a typical design flow for an ASIC or SOC.

As it shows the design flow starts with a specification document that lists out the technical requirements needed in the chip design. It is followed by translating the specification to Architectural design. The architectural design involves designing the functional blocks and the communication protocol between them and translating them into actual modules that contain FSMs, combinational and sequential circuits, etc. The architectural design is then modeled using a Hardware description language like Verilog/VHDL/System Verilog, which is the RTL design stage. The Functional Verification stage starts with a verification plan and a corresponding verification environment that describes and implements the method of proving the design correctness, using different Verification techniques. The design is refined until the HDL model is proved to be meeting the specifications. This stage is followed by Synthesis – a process of transforming the HDL design into a technology-specific gate-level netlist, given all the specified constraints and optimization settings. DFT is a structural technique that facilitates a design to become testable after production. All the works till this stage are normally called as the Frontend of VLSI design and are executed by Frontend Engineers.

The next step in the ASIC Design flow is Placement and Routing which involves arranging approximate locations of a set of modules that need to be placed on a layout. Clock tree synthesis is a process that makes sure that the clock gets distributed evenly to all sequential elements in a design to fix the timing violations. This is followed by routing in which exact paths for the interconnection of standard cells and macros and I/O pins are determined. The file produced at the output of the layout is the GDSII (GDS2) file which is the file used by the foundry to fabricate the silicon. Gate level simulations and Static Timing Analysis (a method of validating the timing performance of a design by checking all possible paths for timing violations without having to simulate) are also done to make sure that the gate-level design meets the timing requirements for correct design operations. All steps after logic synthesis are performed by Backend engineers and form the Backend jobs.

Work of a Frontend Engineer

• RTL Design/Coding
• Synthesis
• Functional Verification
• DFT
• Work of a Backend Engineer
• Floor Planning
• Placement
• Clock Tree Synthesis
• STA
• Physical Verification

Which one has more career Opportunities?

With the advances being made in technologies like process geometries, feature size, and product innovations on a daily basis, there is a constant need to design, develop, and re-engineer integrated circuits (ICs). Since electronic products like mobile phones are being released with new features in shorter cycles, there is a healthy demand for qualified VLSI engineers to work on these products. Therefore, there is a good scope for a career in the VLSI industry.

The important point is that both the domains, front end, and back end have their own advantages and have great career prospects. It is completely up to you which one to choose depending on your interest and confidence level, as both offer a great deal of learning and growth.

How to choose?

In order to become a front end engineer, one needs to have good knowledge of HDLs(Verilog/VHDL/SystemVerilog). It will be an added advantage if you have industry related protocol knowledge.

So if you have ample digital fundamental knowledge, are fond of HDL coding, love debugging, and want to have a sound understanding about the functionality of IC or chip you should definitely go for Front End. With the recent emergence of Artificial intelligence and its application towards VLSI opens up huge scope for Front end engineers.

In order to become a back end engineer, one needs to be well equipped with the concepts of digital electronics, CMOS and Analog Circuits, Scripting knowledge for automation, Hands-on Tools for physical design, layout, etc.

If the above-mentioned skills fascinate you then you can opt for Backend and there might be a chance to work in Foundry as well.

Challenges faced by a fresher to get into the VLSI industry

Even though the VLSI industry is a niche and has lots of career opportunities, on the flip side, the industry is currently somewhat less reachable for fresh graduates, compared to other areas due to some particular reasons. Firstly, VLSI or chip design requires a deeper level of knowledge and skills than other electronics-related fields. But our Universities are not catering 100% to the VLSI industry requirements. Secondly, VLSI chip design is expensive and requires access to high-cost, specialized electronic design automation (EDA) tools.

How can Chipedge help?

Chipedge offers various courses for fresh graduates both in frontend and backend domains, to choose from. The courses are well structured starting from building a strong foundation by emphasizing fundamental subjects like Digital, CMOS, etc. Once the candidate becomes confident with the fundamental knowledge, we impart all the domain-specific skills required for the VLSI industry, by giving hands-on training on industry-standard EDA tools (Synopsys).